The present invention relates to a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix.
FIG. 25 shows a circuit configuration of a ferroelectric memory common to first and second conventional examples and embodiments of the present invention. As shown in FIG. 25, a ferroelectric memory cell is of a one-transistor one-capacitor type having one transistor and one ferroelectric capacitor. A gate electrode of the transistor of the ferroelectric memory cell is connected to a word line and a drain electrode of the transistor is connected to a bit line. One electrode of the capacitor of the ferroelectric memory cell is connected to a plate line and the other electrode of the capacitor is connected to a source electrode of the transistor. Thus, the ferroelectric memory cell is controlled by signals applied to the plate line, the word line and the bit line.
(First conventional example)
Hereinafter, a ferroelectric memory of the first conventional example will be described with reference to FIGS. 26, 27 and 28.
FIGS. 26 and 27 show a layout of a ferroelectric memory cell array in the first conventional example, and FIG. 28 shows a cross-sectional structure taken along line Dxe2x80x94D of FIGS. 26 and 27. Note that FIG. 27 is a view showing only active regions, word lines, bit line contacts and storage node contacts taken from the layout of FIG. 26.
Referring to FIGS. 26, 27 and 28, the reference numerals 11a, 11b, 11c and 11d denote plate lines constructed of upper electrodes of ferroelectric capacitors. The reference numerals 12a, 12b, 12c and 12d denote word lines made of polycrystalline silicon constructed of gate electrodes of access transistors. The reference numerals 13a, 13b, 13c and 13d denote bit lines made of aluminum interconnections. The reference numerals 14a, 14b, 14c and 14d denote storage nodes of ferroelectric memory cells, each constructed of a lower electrode of the ferroelectric capacitor. The reference numeral 18 denotes a one-bit ferroelectric memory cell of the one-transistor one-capacitor type, and the reference numeral 19 denotes a transistor constituting the ferroelectric memory cell 18. The reference numeral 15 denotes storage node contacts connecting the storage nodes 14a, 14b, 14c and 14d and active regions 16 of the transistors 19, and the reference numeral 17 denotes bit line contacts connecting the bit lines 13a, 13b, 13c and 13d and the active regions 16 of the transistors 19.
Referring to FIG. 26, the reference code a1 denotes the first inter-plate distance between the adjacent plate lines 11a and 11b with the bit line contacts 17 therebetween, b1 denotes the line width of the plate lines 11a and 11b including the storage nodes 14a, and c1 denotes the second inter-plate distance between the adjacent plate lines 11b and 11c without the bit line contacts 17 therebetween.
As shown in FIG. 26, the storage node contact 15 and the bit line contact 17 are placed at the shortest distance from each other via the active region 16.
(Second conventional example)
Hereinafter, a ferroelectric memory of the second conventional example will be described with reference to FIGS. 29, 30 and 31.
FIGS. 29 and 30 show a layout of a ferroelectric memory cell array in the second conventional example, and FIG. 31 shows a cross-sectional structure taken along line Exe2x80x94E of FIGS. 29 and 30. Note that FIG. 30 is a view showing only active regions, word lines, bit line contacts and storage node contacts taken from the layout of FIG. 29.
Referring to FIGS. 29, 30 and 31, the reference numerals 21a, 21b, 21c and 21d denote plate lines constructed of upper electrodes of ferroelectric capacitors. The reference numerals 22a, 22b, 22c and 22d denote word lines made of polycrystalline silicon constructed of gate electrodes of access transistors. The reference numerals 23a, 23b, 23c and 23d denote bit lines made of aluminum interconnections. The reference numerals 24a, 24b, 24c and 24d denote storage nodes of ferroelectric memory cells, each constructed of a lower electrode of the ferroelectric capacitor. The reference numeral 28 denotes a one-bit ferroelectric memory cell composed of one transistor and one capacitor, and the reference numeral 29 denotes the transistor constituting the ferroelectric memory cell 28. The reference numeral 25 denotes storage node contacts connecting the storage nodes 24a, 24b, 24c and 24d and active regions 26 of the transistors 29, and the reference numeral 27 denotes bit line contacts connecting the bit lines 23a, 23b, 23c and 23d and the active regions 26 of the transistors 29.
Referring to FIG. 29, the reference code a2 denotes the first inter-plate distance between the adjacent plate lines 21a and 21b with the bit line contacts 27 therebetween, b1 denotes the line width of the plate lines 21a and 21b including the storage nodes 24a, and c1 denotes the second inter-plate distance between the adjacent plate lines 21b and 21c without the bit line contacts 17 therebetween. The reference code d denotes the distance between one side edge of the word line 22a and the center of the bit line contact 27, e denotes the line width of the word line 22a, and f denotes the distance between the other side edge of the word line 22a and the center of the storage node contact 25. The first inter-plate distance a2 in the second conventional example is not the shortest distance obtainable by machining the plate lines 21a and 21b. 
The distance between the storage node contact 25 and the bit line contact 27 is set to be the shortest via the active region 26, which is the sum of the line width e of the word line 22a, the distance d between one side edge of the word line 22a and the center of the bit line contact 27, and the distance f between the other side edge of the word line 22a and the center of the storage node contact 25.
(Problems of the first conventional example)
In the first conventional example, the length L11 of the ferroelectric memory cell 18 in the bit line direction satisfies L11=a1/2+b1+c1/2.
Therefore, the area S11 of the ferroelectric memory cell 18 is represented by
S11=L11xc3x97W11=(a1/2+b1+c1/2)xc3x97W11
wherein W11 is the length of the ferroelectric memory cell 18 in the word line direction.
In general, a predetermined space is required between the edge of the plate line 11a, 11b, 11c or 11d on the side of the bit line contacts and the bit line contacts for prevention of short-circuiting therebetween. For this reason, the first inter-plate distance a1 between the adjacent plate lines 11a and 11b with the bit line contacts 17 therebetween is greater than the second inter-plate distance c1 between the adjacent plate lines 11b and 11c without the bit line contacts 17 therebetween, that is, a1 greater than c1.
Therefore, in the first conventional example, the area S11 of the ferroelectric memory cell 18 disadvantageously increases compared with the case in which all the inter-plate distances are equal to the second inter-plate distance c1, that is, a1=c1.
In addition, in the first conventional example, in order to drive the plate line 11a for read/write of data from/in the ferroelectric memory cell 18, all of the bit lines 13a, 13b, 13c and 13d connected to the plate line 11a via the word line 12a are used simultaneously. In this occasion, since the bit lines 13a, 13b, 13c and 13d are adjacent to each other, noise is generated due to the capacitance existing between the bit lines, and this may easily cause a malfunction.
(Problems of the second conventional example)
In the second conventional example, the length L12 of the ferroelectric memory cell 28 in the bit line direction satisfies L12=d+e+f+b1/2+c1/2.
Since the minimum value of the first inter-plate distance a2 between the adjacent plate lines 21a and 21b with the bit line contacts 27 therebetween is equal to the first inter-plate distance al in the first conventional example, the following relationship is satisfied.
d+e+f=a2/1+b1/2 greater than a1/2+b1/2
From this relationship and the relationship a1 greater than c1 described in the first conventional example, the following relationship is satisfied.
d+e+f=a2/1+b1/2 greater than c1/2+b1/2.
As a recent tendency, the operating voltage has been increasingly made lower with achievement of finer semiconductor devices. Ferroelectric capacitors however fail to operate sufficiently with a low voltage. Therefore, a voltage higher than the operating voltage for the surrounding circuits must be applied to the ferroelectric capacitors. In consideration of this, as transistors constituting ferroelectric memory cells, it is necessary to use transistors having a larger gate length and operating with a higher voltage, compared with transistors for the surrounding circuits.
However, in the second conventional example, if the gate length (the line width e of the word line 22a) is made large, the area of the ferroelectric memory cell 28 and thus the area of the ferroelectric memory cell array disadvantageously increase.
In view of the above, a first object of the present invention is reducing the area of ferroelectric memory cells, and the second object is preventing the area of ferroelectric memory cells from increasing even when the gate length of transistors is made large.
To attain the first object, the first ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells, bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction, cut portions are formed at positions of the plate lines near the bit line contacts, and the active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.
According to the first ferroelectric memory, cut portions are formed at positions of the plate lines near the bit line contacts, and the active regions of the transistors extend in directions intersecting with the word line direction and the bit line direction. Therefore, since the length of the memory cells in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the first conventional example.
To attain the first object, the second ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction among the plurality of memory cells are placed at positions offset from each other in the bit line direction, a word line is placed in common for the transistors of the set of memory cells, a plate line is placed in common for the ferroelectric capacitors of the set of memory cells, and bit line contacts each for connecting a bit line and an active region of the transistor are placed between the plate lines adjacent to each other in a bit line direction.
According to the second ferroelectric memory, ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction are placed at positions offset from each other in the bit line direction. Therefore, the length of the memory cell in the word line direction is greatly reduced compared with the first conventional example. In addition, a plate line is placed in common for the ferroelectric capacitors of the set of memory cells, and bit line contacts are placed between the plate lines. Therefore, the length of the memory cell in the bit line direction increases only by a rate smaller than the reciprocal of the rate of reduction of the length of the memory cell in the word line direction, with respect to the first conventional example. Thus, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the first conventional example.
To attain the first object, the third ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction among the plurality of memory cells are placed at positions offset from each other in the bit line direction, a word line is placed in common for the transistors of the set of memory cells, plate lines are placed separately for the respective ferroelectric capacitors of the set of memory cells, and bit line contacts each for connecting a bit line and an active region of the transistor are placed between plate line groups each composed of the plurality of plate lines corresponding to the set of memory cells.
According to the third ferroelectric memory, ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction are placed at positions offset from each other in the bit line direction. Therefore, the length of the memory cell in the word line direction is greatly reduced compared with the first conventional example. In addition, bit line contacts are placed between plate line groups each composed of the plurality of plate lines corresponding to the set of memory cells. Therefore, the length of the memory cell in the bit line direction increases only by a rate smaller than the reciprocal of the rate of reduction of the length of the memory cell in the word line direction, with respect to the first conventional example. Thus, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the first conventional example.
In the third ferroelectric memory, plate lines are placed separately for the respective ferroelectric capacitors of the set of memory cells. Therefore, although the length of the memory cell in the bit line direction is larger compared with the second ferroelectric memory, the bit lines for sending signals to the ferroelectric capacitors of the set of memory cells do not share the same plate line. This prevents generation of noise due to the capacitance existing between the bit lines, and thus prevents occurrence of a malfunction due to noise.
To attain the first object, the fourth ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction among the plurality of memory cells are placed at positions offset from each other in the bit line direction, a plate line is placed in common for the ferroelectric capacitors of the set of memory cells, and bit line contacts each for connecting a bit line and an active region of the transistor are placed on both sides of the plate line in the bit line direction.
According to the fourth ferroelectric memory, ferroelectric capacitors of one set of memory cells adjacent to each other in the word line direction are placed at positions offset from each other in the bit line direction. Therefore, the length of the memory cell in the word line direction is greatly reduced compared with the first conventional example. In addition, a plate line is placed in common for the ferroelectric capacitors of the set of memory cells, and bit line contacts are placed on both sides of the plate line in the bit line direction. Therefore, the length of the memory cell in the bit line direction increases only by a rate smaller than the reciprocal of the rate of reduction of the length of the memory cell in the word line direction, with respect to the first conventional example. Thus, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the first conventional example.
To attain the second object, the fifth ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein active regions of the transistors of the plurality of memory cells extend through between the ferroelectric capacitors in the bit line direction, and word lines include: gate electrodes having a relatively large width formed above portions of the active regions extending through between the ferroelectric capacitors in the bit line direction; and interconnections of the ferroelectric capacitors having a relatively small width and extending in the bit line direction.
According to the fifth ferroelectric memory, word lines include: gate electrodes having a relatively large width formed above portions of the active regions extending through between the ferroelectric capacitors in the bit line direction; and interconnections of the ferroelectric capacitors having a relatively small width and extending in the bit line direction. Therefore, it is possible to form the word lines so that both the gate electrodes and the interconnections of the word lines do not protrude from the regions of the plate lines running in the word line direction even when the gate length of the transistors is set equal to the gate length of the transistors in the second conventional example. Therefore, since the length of the memory cell in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the second conventional example.
To attain the second object, the sixth ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors adjacent to each other in the bit line direction with a bit line contact therebetween among a plurality of ferroelectric capacitors constituting the plurality of memory cells are placed not to be offset from each other in the word line direction, while ferroelectric capacitors adjacent to each other in the bit line direction without a bit line contact therebetween among the plurality of ferroelectric capacitors constituting the plurality of memory cells are placed at positions offset from each other in the word line direction, active regions of the transistors of the plurality of memory cells extend through in the bit line direction between the ferroelectric capacitors adjacent to each other in the word line direction, and word lines include: gate electrodes having a relatively large width formed above the active regions; and interconnections of the ferroelectric capacitors having a relatively small width and extending in the bit line direction.
According to the fifth ferroelectric memory, word lines include: gate electrodes having a relatively large width formed above the active regions; and interconnections of the ferroelectric capacitors having a relatively small width and extending in the bit line direction. Therefore, it is possible to form the word lines so that both the gate electrodes and the interconnections of the word lines do not protrude from the regions of the plate lines running in the word line direction even when the gate length of the transistors is set equal to the gate length of the transistors in the second conventional example. Therefore, since the length of the memory cell in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the second conventional example.
To attain the second object, the seventh ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors of a pair of memory cells adjacent to each other in the word line direction among the plurality of memory cells are placed at positions offset from each other in the bit line direction, a plate line is placed in common for the ferroelectric capacitors of the pair of memory cells, and a word line is placed in common for the transistors of the pair of memory cells and formed between the ferroelectric capacitors of the pair of memory cells.
According to the seventh ferroelectric memory, a plate line and a word line are placed in common for the ferroelectric capacitors of the pair of memory cells, and the word line is formed between the ferroelectric capacitors of the pair of memory cells. Therefore, since the length of the memory cell in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the second conventional example, even when the gate length of the transistors is set equal to the gate length of the transistors in the second conventional example.
In the seventh ferroelectric memory, the line width of the word line is preferably set equal to or smaller than the distance between the ferroelectric capacitors of the pair of memory cells.
By the above setting, the length of the memory cell in the bit line direction can be made further small, and therefore the area of the memory cell and thus the area of the memory cell array can be further reduced.
To attain the second object, the eighth ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein ferroelectric capacitors of pairs of memory cells adjacent to each other in the word line direction among the plurality of memory cells are placed at positions offset from each other in the bit line direction, active regions of the transistors of ones of the pairs of memory cells extend through between the ferroelectric capacitors of the others of the pairs of memory cells in the bit line direction, intersecting with a plate line for the other memory cells, first word lines are provided for the transistors of the ones of the pairs of memory cells, while second word lines are provided for the transistors of the other memory cells, and the second word lines are narrowed at portions intersecting with the active regions of the transistors of the ones of the pairs of memory cells to a degree that the active regions are prevented from being turned to an OFF state.
According to the eighth ferroelectric memory, the second word lines are narrowed at portions intersecting with the active regions of the transistors of the ones of the pairs of memory cells to a degree that the active regions are prevented from being turned to an OFF state. Therefore, since the length of the memory cell in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the second conventional example, even when the gate length of the transistors is set equal to the gate length of the transistors in the second conventional example.
To attain the second object, the ninth ferroelectric memory of the present invention is a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix, wherein bit lines are composed of active regions running through in the bit line direction between the ferroelectric capacitors of pairs of memory cells adjacent to each other in the word line direction among the plurality of memory cells, and provided integrally with active regions of the transistors of the plurality of memory cells, and word lines include: interconnections having a small width formed above the bit lines to prevent the bit lines from being turned to an OFF state; and gate electrodes having a width larger than the interconnections formed above the active regions of the transistors.
According to the ninth ferroelectric memory, word lines include: interconnections having a small width formed above the bit lines to prevent the bit lines from being turned to an OFF state; and gate electrodes having a width larger than the interconnections formed above the active regions of the transistors. Therefore, since the length of the memory cell in the bit line direction can be made small, the area of the memory cell and thus the area of the memory cell array can be reduced, compared with the second conventional example, even when the gate length of the transistors is set equal to the gate length of the transistors in the second conventional example.